Cadence has announced the successful tapeout of its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution. Developed on the TSMC N3P process, the technology achieves per-lane speeds of 64Gbps, targeting the connectivity requirements of high-performance computing (HPC), artificial intelligence, and advanced data center systems.
As semiconductor design moves toward 3nm nodes and below, developers are increasingly required to balance power, performance, and area (PPA) with reliable die-to-die communication. This UCIe-compliant solution is engineered to address these requirements by leveraging TSMC’s N3P technology to maintain power efficiency within aggressive energy budgets.
The 64Gbps performance levels enable significant bandwidth density, reaching 3.6Tbps/mm in standard packaging and 21.08Tbps/mm in advanced packaging configurations. To facilitate integration across various platforms, including networking appliances and AI accelerators, the IP subsystem supports a variety of interface protocols such as AXI, CXS.B, CHI-C2C, PCIe, and CXL.
The architecture incorporates advanced error correction, lane margining, and diagnostic tools to ensure operational stability in heterogeneous multi-die environments. Additionally, the system features self-calibrating capabilities and hardware-based bring-up, which allows for system initialization without the need for firmware intervention. The design also utilizes a streamlined clocking scheme with an integrated phase-locked loop (PLL) to maintain performance across fluctuating voltage and temperature conditions.
“Cadence has been at the forefront of die-to-die interface solutions since our first tapeout in 2018. Pivoting to UCIe in 2022, we have extensively demonstrated silicon proofs of our Gen 1 and Gen 2 UCIe solutions over the past two years,” said Arif Khan, vice president of marketing in the Silicon Solutions Group at Cadence. “Given the insatiable demand for throughput and efficiency driven by AI and HPC applications, we are proud to make our third-generation UCIe IP—achieving speeds of 64G—available. By collaborating with our trusted partner, TSMC, we are bringing a high-quality and efficient solution to our mutual customers.”
By achieving this milestone, Cadence aims to support the development of scalable multi-die systems and the growth of multi-vendor chiplet ecosystems.
